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mrhat
10-26-2001, 12:33 PM
For those who ever wondered about those darnded little chips here are the list and totals.
CommTech Chips With Numbers

Character Names & Numbers

Classic Trilogy (10 Total)

Jawa C1
R2-D2 with "Holographic" Princess Leia C2
Luke Skywalker C3
Greedo C4
Han Solo C5
Darth Vader C6
Stormtrooper C7
Princess Leia Organa C8
Admiral Motti C9
Wuher C11

Episode 1 (51 Total, or 54 with all varients of the battle droids)

Qui-Gon Jinn 1
Obi-Wan Kenobi 2
Anakin Skywalker 3
Padme Naberrie 4
Jar Jar Binks 5
Queen Amidala 6
R2-D2 7
C-3PO 8
CommTech Reader 9
Captian Panaka 10
Ric Olie 11
Queen Amidala Couriscant 12
Anakin Skywalker Jedi 13
Qui-Gon Jinn Naboo 14
Obi-Wan Kenobi Naboo 15
Naboo Foot Soldier 16
Qui-Gon Jinn Jedi Master 17
Senator Palpatine 18
Obi-Wan Kenobi Jedi Master 19
Mace Windu 20
Yoda 21
Gasgano 22
Ody Mandrell 23
Boss Nass 25
Captain Tarpels 26
Ki-Adi-Mundi 28
Adi Gallia 29
Naboo Royal Guard 30
Darth Sidous 31
Darth Maul 32
Nute Gunray 33
Rune Haako 34
Battle Droid 35
Watto 36
OOM-9 37
Destroyer Droid Battle Damage 38
Chancellor Valorum 41
Darth Maul Tatooine 43
R2-B1 44
Darth Maul Sith Aprentice 45
Destroyer Droid 46
Sio Bibble 50
Pit Droids 51
Swimming Jar Jar Binks 56
Queen Amidala Theed Invasion 71
Anikin Skywalker Naboo Pilot 72
Darth Sidious as Hologram 73
TC-14 74
Watto's Box 113
Tatooine Showdown 114
Mos Espa Encounter 115

TOTAL; 61 Chips or 64 with those droids.

FOR THOSE WHO EVER WANTED TO KNOW

bigbarada
10-26-2001, 01:19 PM
Who was supposed to be the C10 COMMTECH chip? I'm assuming it was either Chewie Dejarik, Ben Kenobi, Tusken Sniper or Jek Porkins. Since they were all shown with COMMTECH chips in prototype form.

master jedi
10-26-2001, 03:43 PM
I wonder who was supposed to be
24
27
39
40
42
47
48
49
52
53
54
55
57-70
75-112

for the episode 1 line.

mrhat
10-26-2001, 03:44 PM
Actually youre probobly right, seeing as they skip a whole bunch of #'s 74 to 113??? they were definatly going to make those advanced ones to finish out the set. Unfortunetly we will never see the likes of CommTech Agian...

Mandalorian Candidat
10-26-2001, 07:40 PM
Thanks for the list. I hope they eventually make a comeback or are at least resurrected in a similar, but much improved, format.

GNT
10-26-2001, 10:52 PM
Originally posted by master jedi
I wonder who was supposed to be
24
27
39
40
42
47
48
49
52
53
54
55
57-70
75-112

Lucky for you guys I keep my sheet that had them listed,these came from those Hasbro Sheets that had them listed,alot of time went into finding and piecing them together back then :)

and yes Chewbacca was meant to be No.10 for the Classic Line :)

24 - Unknown
27 - Unknown
39 - Gungan Warrior
40 - Lott Dod
42 - Unknown
47 - Tusken Raider
48 - Security Battle Droid
49 - Unknown
52 - Nute Gunray - Holograph (the clear Nute figure we've seen)
53 - Coruscant Guard
54 - Mas Amedda
55 - Obi Wan - Naboo Swamp (chocolate Obi)
57- R2-D2 - Name reveal(Naboo Escape )
58 - Unknown
59 - Unknown
60 - Sabe
61 - Jar Jar Binks - Mechanic
62- Unknown
63 - Unknown
64 - Qui-Gon -Battle Worn (Mos Espa Disguise)
65 - Unknown
66 - Anakin - Mechanic
67 - Shmi Skywalker
68 - Sebulba
69 - Unknown
70 - Unknown
71 - Queen Amidala - Battle
72 - Anakin - Naboo Pilot
73 - Darth Sidious - Hologram
74 - Tc-14
75 - Boss Nass - Naboo Temple (Gungan Sacred Place)
76 - Fode and Beed
77- Unknown
78 - Darth Maul - Generator Duel (Final Duel)
79-113 - Unknown

As you can see most of them have been made in the POTJ line

r2dee2
10-27-2001, 02:51 AM
Here's my list of the CTC's, including the holo and white CTC numbers (http://fan.starwars.com/ListForce/files/CTCnumbers.htm)

mrhat
10-27-2001, 11:41 AM
Thats a reat list, but you forgot the 3 packs!!! not that it matters they all came on holo back except Tattoine Showdown. iBelieve. we will never know the true potential of these chips however...

bigbarada
10-27-2001, 11:53 AM
I thought the CTC were a great idea, that was limited by technology at the time. I remember spending hours (ok, maybe several minutes) just trying out every figure and seeing how they interacted.

I would love to see the idea resurrected but with significantly improved technology.

r2dee2
10-27-2001, 12:31 PM
Ah, mrhat, my fellow Colorado-an, check the list again....the cinema scenes are there...

CS Tatooine Showdown 113 H W B
CS Watto's Box 114 H W B
CS Mos Espa Encounter 115 H W B

....and they all came with both the holo and whites backs, if I'm not mistaken. Thrawn also has a list here (http://www.figures.com/Features/index.html?show_article=21063&domain=sirstevesguide.com&dom=ss&domain_id=5) and he's added a few more of the Euro figures that came with the CommTalk chips....

COMMTalk - Europe

Obi-Wan Kenobi (Naboo)
Qui-Gon Jinn (Naboo)
Battle Droid
Jar Jar Binks

that were first released with the holo chips and were recently found with the white chips.

sith_killer_99
10-29-2001, 02:21 AM
I would eventually like to get all of the CT's holo and white backs!

It shouldn't be too difficult since I collect both carded and loose. I do have most of them already.;)

I am wondering about the Foreign chips though. How many languages were made? I know they put out French and Spanish. But which ones were produced and in which languages?:confused:

BTW, do the foreign chips have the same numbers as the US versions?

evenflow
10-29-2001, 08:44 AM
I wonder who all those unknowns were goingt o be ?

r2dee2
10-29-2001, 10:38 AM
evenflow, Thrawn has a list here (http://www.figures.com/Features/index.html?show_article=21062&domain=sirstevesguide.com&dom=ss&domain_id=5) of the CTC numbers, including the ones not produced. Interesting list:)

I know of the French and Spanish chips as well, but actually I don't know if there are any other languages. I do know the Spanish chip I have of my Padme figure, has the same number on the back as my US Padme figure, so I'd think the numbers are probably the same....even though the back of the foreign chip is a little different than the US version. Whereas the US has the name, number and status , the foreign one only has the name and number.

It is fun listening to the foreign chips too:D

evenflow
10-29-2001, 10:43 AM
Cool, still a few numbers missing though. Wonder who they would have been.

master jedi
10-29-2001, 07:18 PM
Originally posted by evenflow
Cool, still a few numbers missing though. Wonder who they would have been.

They probably would've been resculpts of Obi-Wan.

GNT
10-30-2001, 02:55 AM
Originally posted by r2dee2
evenflow, Thrawn has a list here (http://www.figures.com/Features/index.html?show_article=21062&domain=sirstevesguide.com&dom=ss&domain_id=5) of the CTC numbers, including the ones not produced. Interesting list:)

I posted the list above,which nobody saw :rolleyes: plus thrawns list has a few errors like:


116 - Pit Droids *

Which was never going to be a Cinema Scene as these were to be released in the foreign 2packs to replace the Battle Droids,so no Commtech chip!!!!!!

Darth Ludicrous
11-27-2001, 02:16 PM
You could also make the case that C12 would have been the tan robed old Obi-Wan, and C13 would have been Jek Porkins (or vice versa). They were also hold-overs from the 2000 line along with Dejarik Chewie.

If you want to see which figures would have been Commtech, had the line continued, check out the Toy Fair 2000 pics here:

http://www.starwars.com/collecting/news/2000/02/news20000215.html

Kind of a fun blast from the past!

OC47150
12-06-2001, 05:08 PM
I'll be honest, the commchips were a nice try at something different but the technology just wasn't up to snuff. I used my chips as stands until I bought a boatload of Action Stands last month.

JediTricks
12-07-2001, 05:24 AM
Originally posted by OC47150
I'll be honest, the commchips were a nice try at something different but the technology just wasn't up to snuff. I used my chips as stands until I bought a boatload of Action Stands last month. I disagree, I think the technology WAS up to snuff, but Hasbro was too cheap to use the 2nd, more advanced audio processor instead of the cheapy lower version one. They jumped the gun for no reason.

snakeplkn
12-07-2001, 12:09 PM
Does anyone know of a webpage explaining the technology behind the COMMTech?

Once I took a COMMTech reader apart and it reminded me a lot of "E-ZPass" devices used when driving through toll booths. The area where the chip was to be passed over was a coil. If I remember my high school science correctly, electricity in the coil creates a magnetic field. When the chip passes over the field, it energizes the chip via the field to send out a signal to the COMMTech's transponder. The particular signal is read and given to the COMMtech's harddrive where the necessary sound is pulled up and sent to the speaker. If this is so, concerning the unproduced chips, the sounds should already be on the harddrive.
It would only be a matter of decoding the current chip signals and using that as a basis to find the new ones.

Or I could be wrong.

Snake Plissken
"A little human compassion"

jedi master sal
12-07-2001, 12:34 PM
Thanks to all of you who contributed lists. I have been looking for awhile trying to unravel this mystery myself. Nice to know I got friends out there like you.

JediTricks
12-08-2001, 01:15 AM
Hasbro has guarded the secret of the chips, but I believe the chips contain the recorded data, not the reader. I read the patent info that was filed for these and I think there's a small harmonically-resonated crystal in the chip which sends a small, highly compressed file that contains the vocorded data to the reader. The reader has 2 processors, one that mimics human speach and has a very low range of sounds it can mimic, and the more advanced one that mimics a much broader range of sounds and doesn't cut out as much of the sound's audio pattern.

Since you mentioned coils, it's possible it's resistors instead of a low-frequency crystal system, but I'm stil confident that the reader doesn't have the chip data on-board.

OC47150
12-09-2001, 01:23 PM
JediTricks, you know way too much info about the commchips!

Darth Ludicrous
12-12-2001, 03:23 PM
Another failing (besides the technology) was a lack of creativity in devising the housing for the reader/chip system. Hasbro should have embedded the reader in vehicle(s) or playset(s), and the chips in the chest cavities of the figures (ala Playmates' Simpsons line or Jakks Pacific's "Titan Tron"). This would have made the toys themselves "interact", as opposed to making the rather superfluous accessories we ended up with interactive.

JediTricks
12-13-2001, 11:59 PM
Originally posted by OC47150
JediTricks, you know way too much info about the commchips! There was a time when this was hotly debated, so I did a bit of research and speculation and came up with some theories, which got hashed out and boiled down and compared to patent information descriptions. I think the technology is really cool, so it was easy to get into a discussion about back in the day.

Marsguo
01-10-2002, 12:54 PM
@ snakeplkn : harddrive bwaahaaahaa :crazed:
There are some sounds integrated into the reader like the lightsaber sound and the laserblast , but the other ones really come from the chips.

There were also German languge versions of the chips, they even had a different name , CommTalk .

@ JediTricks : Too bad there weren´t more people who thought the commtech technology is cool when websites were starting petitions to stop Hasbro from selling the figures with the chips. :(

@ Darth Ludicrous : Yeah , it would have been better if they included the chip inside the figure s . :cool:

I think the first chips were really bad , e.g. OOM-9 , but others sound nice like the R2D2/HoloLeia or the Pitdroids. I wonder why they weren´t able to take sound from the actual movie.

Mandalorian Candidat
01-10-2002, 10:11 PM
I really liked the idea of the CTs. It's too bad they got scrapped. Hasbro should have done a better job on them voice wise as well as leaving off all the multiple lightsaber noises. How many of those did we need.

I wonder how much the figures would have cost if Hasbro had gone with the better chip technology.

sith_killer_99
02-05-2002, 05:04 AM
r2dee2, HELP!?!?!

I can't get your link to work anymore. I wanted to make a list of all the CommTech chip variations. Holo, White, Both, etc.

Can you post the link again?

Rollo Tomassi
02-05-2002, 07:48 AM
I agree that Hasbro dropped the ball/screwed the pooch. If they had been thinking long term instead of worrying about 2nd quarter sales, they would have done a little more R&D and produced some truly awesome CTC technology which would have set the standard for toys in the years to come. But instead, they let the Brand Name Star Wars carry some cheap junk into their wallets.

brentfett
04-04-2002, 02:28 PM
Ditch those things and lower the prices!

SirSteve
04-04-2002, 02:42 PM
I'd really like to get an archive of all the audio in mp3 format. Anyone game?

:)

fourtwo
04-04-2002, 02:56 PM
that would be just out of hand. think of all the other languages and what not. if i can figure out how to get a decent quality rip of it i'll be in to sharing what i have with the site.

jedi_uk73
04-04-2002, 04:40 PM
Did you know that there was also an un-numbered comtech chip. It was a UK promotion chip that had an Episode I logo on BOTH sides.

Vocals were.

' Your destiny now lies with me' - Sidious
' You will be a jedi, I promise ' - Obi Wan
' Greed can be a powerfull ally ' - Qui Gon

sith_killer_99
04-04-2002, 06:35 PM
Yep, I've seen the chip up close. I still want to get one for my collection.

I love those wacky foreign (non-US) SW items. ;)

jedi_uk73
04-05-2002, 06:54 AM
Hi sith_killer_99

That UK comtech chip can be bought from www.thetoyshop.com

Its a UK company, I'm sure they ship overseas. It only costs £4 + p&p.

Not bad for a promo item.

JEDIpartner
04-05-2002, 09:29 AM
That's quite reasonable!!!

Taichi
04-06-2002, 12:03 PM
Isn't it weird how we hated the Commtech chips when they first came out, but now that our figures don't come with stands, we long for them again???

I'm guilty too.....don't get me wrong......and I am not trying to blame anybody.....

I'm just saying that we didn't realize what a good thing they were, until we no longer had them.....

187-Maul
04-06-2002, 06:59 PM
getting back to the real question sirsteve, niubniubsuniverse has the commtech lines to download I think, I don't know how many though

Jedi_Rainman
04-13-2002, 05:34 AM
The chips were okay, but I'd rather see videos

swjunk
04-18-2002, 01:42 PM
The chips were the best. They atleast did something. As we say, the elimination of the chips did nothing to the price of the figures. The price of the figures actually jumped up!!!!

Take care,

Matthew

mightywhelk
04-19-2002, 08:51 AM
I only recently bought a CommTech reader for 99p and finally got to hear the voices. I have to say that Adi Gallia sounded like Professor Stephen Hawking! It made me cry laughing!

musasa
05-09-2002, 02:09 AM
Here is a complete list of the diff languages the chips were released on:

English
Spanish
Italian
French
German

r2dee2
05-09-2002, 09:50 AM
Originally posted by sith_killer_99
r2dee2, HELP!?!?!

I can't get your link to work anymore. I wanted to make a list of all the CommTech chip variations. Holo, White, Both, etc.

Can you post the link again?

sith_killer_99, I just now read your post and most likely you already have resolved your question, but in case not, here is the list I had on my web page, which has now moved to a new location, but which currently doesn't have the list you wanted:

These chips originally came with the HOLO background then switched to white background

Jawa POTF
Darth Maul (Jedi Duel) EP1
Darth Maul (Tatooine) EP1
Darth Vader POTF
Greedo POTF
Han Solo POTF
Luke Skywalker POTF
Mace Windu EP1
Mos Espa Encounter EP1
Ody Mandrell w/Pit Droid EP1
OOM-9 EP1
R2-D2 (uncertain) POTF
Stormtrooper POTF
Tatooine Showdown EP1
Watto's Box (Rare) EP1

These chips only come with the white background

Admiral Motti POTF
Anakin Skywalker (Naboo Pilot) EP1
Darth Maul (Sith Lord) EP1 soft goods
Darth Sidious Hologram EP1
Destroyer Droid Battle Damaged EP1
Jar Jar Binks (Naboo Swamp) EP1
Naboo Royal Guard EP1
Obi-Wan Kenobi (Jedi Knight) EP1 soft goods
Pit Droid 2-pack EP1
Princess Leia POTF
Queen Amidala (Battle) w/ascension gun EP1
Qui-Gon Jinn (Jedi Master) EP1
R2-B1 EP1
Sio Bibble EP1
TC-14 EP1
Wuher POTF

These chips only came out with HOLO backgrounds
Adi Gallia
Anakin Skywalker (Naboo)
Anakin Skywalker (Tatooine) backpack
Battle Droids
Boss Nass
C-3PO
Captain Panaka
Captain Tarpals
Chancellor Valorum
Darth Sidious
Destroyer Droid
Gasgano + Pit Droid
Jar Jar Binks
Ki-Adi Mundi
Naboo Royal Security
Nute Gunray
Obi-Wan Kenobi (Jedi Duel)
Obi-Wan Kenobi (Naboo)
Padmé Naberrie
Queen Amidala (Coruscant)
Queen Amidala Naboo
Qui-Gon Jinn (Jedi Duel)
Qui-Gon Jinn (Naboo)
R2-D2 (Booster Rockets)
Ric Olié
Rune Haako
Senator Palpatine
Watto
Yoda

These figures came out in the fat and thin BUBBLE
OOM-9 EP1
Captain Tarpals EP1
Han Solo POTF
R2-D2 (Booster Rockets) EP1

THRAWN still has his list here. (http://systems.figures.com/Features/index.html?show_article=21062&domain=sirstevesguide.com&dom=ss&domain_id=5)

JON9000
05-28-2002, 10:30 PM
I could swear I saw a Mas Amedda on a red Ep1 card with a oval Commtech chip on ebay once. Maybe it was somewhere else- but if it exists i would bet that it is the holy grail of Ep1 figures

scruffziller
05-30-2002, 06:15 PM
Yeah they were suppose to release a series 2 ( i seen the prototypes for them) the chips looked like little surf boards. They were suppose to be for the figs in POTJ series. DARN I liked 'em!!!!!!!!!!!!!!!

N-2PF
06-09-2002, 04:42 PM
( 12 of 33 )


United States Patent
5,850,628
Jeffway, Jr.
December 15, 1998


Speech and sound synthesizers with connected memories and outputs

Abstract

A speech synthesizing circuit includes a speech synthesizing integrated circuit chip and an external memory integrated circuit chip.
The external memory chip may be an audio data storage chip or an audio synthesizing chip. The chips are connected through an
input-output port on each chip, and the microprocessor of the speech synthesizing chip retrieves speech data from the audio data
storage memory of the audio synthesizing chip. Access to the memory of the audio synthesizing chip is accomplished by software
simulations that modify the functions of instructions pre-programmed into the speech synthesizing chip during manufacture. The
preprogrammed instructions cause the address of speech data to be loaded into a speech address register and the software
modifications cause an address to be loaded into the audio synthesizing chip, by which the speech synthesizing chip will retrieve
speech data from external memory at an address stored in the external memory chip. Alternatively, the instructions to deliver data to
the speech synthesizing chip may be programmed into the audio synthesizing chip. A speaker is connected to balanced speaker
driver outputs of the speech synthesizing chip and also to a single-ended speaker driver of the audio synthesizing chip.


Inventors:
Jeffway, Jr.; Robert W. (Leeds, MA)
Assignee:
Hasbro, Inc. (Pawtucket, RI)
Appl. No.:
790541
Filed:
January 30, 1997


U.S. Class:
704/258
Intern'l Class:
G10L 005/02; G10L 003/00
Field of Search:
704/258,272,270,264,223,200 340/384.5,384.4,384.72 381/117 330/262


References Cited [Referenced By]

U.S. Patent Documents
4234761
Nov., 1980
Wiggins, Jr. et al.
704/258.
4449233
May., 1984
Brantingham
704/258.
4581757
Apr., 1986
Cox
704/258.
4675840
Jun., 1987
Raymond et al.
704/200.
4717261
Jan., 1988
Kita et al.
368/63.
4825385
Apr., 1989
Dolph et al.
704/274.
4946391
Aug., 1990
Hawkins et al.
434/201.
4964837
Oct., 1990
Collier
446/409.
4970659
Nov., 1990
Breedlove et al.
704/270.
4992984
Feb., 1991
Busch et al.
365/200.
5047358
Sep., 1991
Kosiak et al.
438/200.
5225618
Jul., 1993
Wadhams
84/602.
5294229
Mar., 1994
Hartzell et al.
434/336.
5393070
Feb., 1995
Best
463/35.
5680512
Oct., 1997
Rabowsky
704/504.



Other References

Sunplus SPC512A Block Diagram and Functional Description.
Texas Instruments Incorportated, Speech Memories Data Manual (TSP60C20, TSP60C80, and TSP60C81), Post
office Box 655303, Dallas, Texas 75243, 1988.
Texas Instruments Incorporated, TMS60C20 User's Manual (excerpts), Post Office Box 655303, Dallas, Texas 75243,
1985.
Texas Instruments Incorporated, TSP50C0x/1x Family Speech Synthesizer Design Manual, Post Office Box 655303,
Dallas, Texas 75243, 1994.


Primary Examiner: Hudspeth; David R.
Assistant Examiner: Storm; Donald L.
Attorney, Agent or Firm: Fish & Richardson P.C.

Claims



1. A speech synthesizing circuit, comprising:

a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an
input/output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated
circuit chip including an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof,
that, when executed, can cause an address to be loaded into the speech address register; and

an external memory integrated circuit chip, the input/output port of the speech synthesizing integrated circuit chip being connected to
the external memory integrated circuit chip;

the programmable memory of the speech synthesizing integrated circuit chip being programmed to cause the microprocessor to
retrieve speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer, the
programmable memory being programmed by providing a software simulation of the instruction that can cause an address to be
loaded into the speech address register, the software simulation causing the address to be loaded into the external memory
integrated circuit chip without reliance on execution of the instruction pre-programmed into the speech synthesizing integrated circuit
chip to load the address.

2. The speech synthesizing circuit of claim 1 wherein the speech synthesizing integrated circuit chip comprises hardware for
connecting to and obtaining data from an external memory.

3. The speech synthesizing circuit of claim 1 wherein the programmable memory of the speech synthesizing integrated circuit chip is
programmed with speech data for speech synthesis by the speech synthesizer.

4. A speech synthesizing circuit, comprising:

a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an
input/output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated
circuit chip including an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof,
that causes an address to be loaded into the speech address register; and

an external memory integrated circuit chip, the input/output port of the speech synthesizing integrated circuit chip being connected to
the external memory integrated circuit chip;

the programmable memory of the speech synthesizing integrated circuit chip being programmed to cause the microprocessor to
retrieve speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer, the
programmable memory being programmed by providing a software simulation of the instruction that causes an address to be
loaded into the speech address register, the software simulation causing the address to be loaded into the external memory
integrated circuit chip,

wherein the external memory integrated circuit chip comprises an audio synthesizing integrated circuit chip having a microprocessor,
an audio synthesizer, an input/output port, and an audio data storage memory.

5. The speech synthesizing circuit of claim 4 wherein the audio synthesizing integrated circuit chip comprises a programmable
memory programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data from the
audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the audio synthesizer of the audio
synthesizing integrated circuit chip.

6. The speech synthesizing circuit of claim 5 wherein the programmable memory of the audio synthesizing integrated circuit chip
comprises the audio data storage memory of the audio synthesizing integrated circuit chip.

7. The speech synthesizing circuit of claim 4 wherein the speech synthesizer of the speech synthesizing integrated circuit chip
processes speech data at a higher efficiency than the audio synthesizer of the audio synthesizing integrated circuit chip processes.

8. The speech synthesizing circuit of claim 7 wherein the speech synthesizer of the speech synthesizing integrated circuit chip
comprises a linear predictive coding synthesizer.

9. The speech synthesizing circuit of claim 8 wherein the speech synthesizing integrated circuit chip is selected from the family of
TSP50C4X, TSP50C1X, and TSP50C3X chips.

10. The speech synthesizing circuit of claim 9 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip.

11. The speech synthesizing circuit of claim 7 wherein the audio synthesizer of the audio synthesizing integrated circuit chip
comprises an adaptive pulse code modulation synthesizer.

12. The speech synthesizing circuit of claim 11 wherein the audio synthesizing integrated circuit chip is selected from the family of
SPC40A, SPC256A, and SPC512A chips.

13. The speech synthesizing circuit of claim 4 wherein:

the speech synthesizing integrated circuit chip comprises a balanced speaker driver having two outputs for connection of a first
speaker impedance between the two outputs;

the audio synthesizing integrated circuit chip comprises a single-ended speaker driver having a single output for connection to a
second speaker impedance; and

a speaker is connected between the two outputs of the balanced speaker driver of the speech synthesizing integrated circuit chip and
is also connected to the single-ended speaker driver of the audio synthesizing integrated circuit chip.

14. A method of combining a speech synthesizing integrated circuit chip with an external memory integrated circuit chip, comprising
the steps of:

providing a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, a programmable memory, an
input/output port, and a speech address register for storing an address containing speech data, the speech synthesizing integrated
circuit chip including an instruction, pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof,
that, when executed, can cause an address to be loaded into the speech address register;

providing the external memory integrated circuit chip;

connecting the input/output port of the speech synthesizing integrated circuit chip with the external memory integrated circuit chip;

programming the programmable memory of the speech synthesizing integrated circuit chip to cause the microprocessor to retrieve
speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer, the programmable
memory being programmed by providing a software simulation of the instruction that can cause an address to be loaded into the
speech address register, the software simulation causing the address to be loaded into the external memory integrated circuit chip
without reliance on execution of the instruction pre-programmed into the speech synthesizing integrated circuit chip to load the
address.

15. A speech synthesizing circuit, comprising:

a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, and a programmable memory, an
input/output port, the speech synthesizing integrated circuit chip including one or more instructions, pre-programmed into the speech
synthesizing integrated circuit chip during manufacture thereof, that, when executed, can obtain speech data located at an address
stored in a speech address register that stores an address at which speech data is located; and

an external memory integrated circuit chip, the input/output port of the speech synthesizing integrated circuit chip being connected to
the external memory integrated circuit chip;

at least one of the integrated circuit chips being programmed to cause speech data to be delivered from the external memory
integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing
a software simulation of execution of the one or more instructions that can obtain speech data located at an address stored in the
speech address register, the software simulation causing speech data to be obtained by the speech synthesizing integrated circuit
chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip without
reliance on execution of the one or more instructions pre-programmed into the speech synthesizing integrated circuit chip to obtain
speech data.

16. The speech synthesizing circuit of claim 15, wherein the programmable memory of the speech synthesizing integrated circuit
chip is programmed to cause speech data to be delivered from the external memory integrated circuit chip to the speech
synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing the software simulation of the one or
more instructions that obtain speech data located at an address stored in the speech address register.

17. The speech synthesizing circuit of claim 15 wherein the speech synthesizing integrated circuit chip comprises hardware for
connecting to and obtaining data from an external memory.

18. The speech synthesizing circuit of claim 15 wherein the programmable memory of the speech synthesizing integrated circuit chip
is programmed with speech data for speech synthesis by the speech synthesizer.

19. The speech synthesizing circuit of claim 15 wherein the speech synthesizing integrated circuit chip comprises the speech
address register.

20. A speech synthesizing circuit, comprising:

a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, and a programmable memory, an
input/output port, the speech synthesizing integrated circuit chip including one or more instructions, pre-programmed into the speech
synthesizing integrated circuit chip during manufacture thereof, that obtain speech data located at an address stored in a speech
address register that stores an address at which speech data is located; and

an external memory integrated circuit chip, the input/output port of the speech synthesizing integrated circuit chip being connected to
the external memory integrated circuit chip;

at least one of the integrated circuit chips being programmed to cause speech data to be delivered from the external memory
integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing
a software simulation of execution of the one or more instructions that obtain speech data located at an address stored in the
speech address register, the software simulation causing speech data to be obtained by the speech synthesizing integrated circuit
chip from the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip,

wherein the external memory integrated circuit chip comprises an audio synthesizing integrated circuit chip having a microprocessor,
an audio synthesizer, an input/output port, and an audio data storage memory.

21. The speech synthesizing circuit of claim 20 wherein the audio synthesizing integrated circuit chip comprises a programmable
memory programmed to cause the microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data from the
audio data storage memory of the audio synthesizing integrated circuit chip for audio synthesis by the audio synthesizer of the audio
synthesizing integrated circuit chip.

22. The speech synthesizing circuit of claim 21 wherein the programmable memory of the audio synthesizing integrated circuit chip
comprises the audio data storage memory of the audio synthesizing integrated circuit chip.

23. The speech synthesizing circuit of claim 20 wherein the speech synthesizer of the speech synthesizing integrated circuit chip
processes speech data at a higher efficiency than the audio synthesizer of the audio synthesizing integrated circuit chip processes.

24. The speech synthesizing circuit of claim 23 wherein the speech synthesizer of the speech synthesizing integrated circuit chip
comprises a linear predictive coding synthesizer.

25. The speech synthesizing circuit of claim 24 wherein the speech synthesizing integrated circuit chip is selected from the family of
TSP50C4X, TSP50C1X, and TSP50C3X chips.

26. The speech synthesizing circuit of claim 25 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip.

27. The speech synthesizing circuit of claim 23 wherein the audio synthesizer of the audio synthesizing integrated circuit chip
comprises an adaptive pulse code modulation synthesizer.

28. The speech synthesizing circuit of claim 23 wherein the audio synthesizing integrated circuit chip is selected from the family of
SPC40A, SPC256A, and SPC512A chips.

29. The speech synthesizing circuit of claim 20 wherein:

the speech synthesizing integrated circuit chip comprises a balanced speaker driver having two outputs for connection of a first
speaker impedance between the two outputs;

the audio synthesizing integrated circuit chip comprises a single-ended speaker driver having a single output for connection to a
second speaker impedance; and

a speaker is connected between the two outputs of the balanced speaker driver of the speech synthesizing integrated circuit chip and
is also connected to the single-ended speaker driver of the audio synthesizing integrated circuit chip.

30. A method of combining a speech synthesizing integrated circuit chip with an external memory integrated circuit chip, comprising
the steps of:

providing a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, and a programmable
memory, an input/output port, the speech synthesizing integrated circuit chip including one or more instructions, pre-programmed
into the speech synthesizing integrated circuit chip during manufacture thereof, that, when executed, can obtain speech data located
at an address stored in a speech address register that stores an address at which speech data is located;

providing the external memory integrated circuit chip;

connecting the input/output port of the speech synthesizing integrated circuit chip with the external memory integrated circuit chip;

programming at least one of the integrated circuit chips to cause speech data to be delivered from the external memory integrated
circuit chip to the speech synthesizing integrated circuit chip for speech synthesis by the speech synthesizer, by providing a software
simulation of execution of the one or more instructions that can obtain speech data located at an address stored in the speech
address register, the software simulation causing speech data to be obtained by the speech synthesizing integrated circuit chip from
the external memory integrated circuit chip at an address stored in the external memory integrated circuit chip without reliance on
execution of the one or more instructions pre-programmed into the speech synthesizing integrated circuit chin to obtain speech data.

31. A speech synthesizing circuit, comprising:

a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, and an input/output port for interfacing
with an external memory; and

a sound synthesizing integrated circuit chip having a microprocessor, a sound synthesizer having a data rate substantially greater
than that of the speech synthesizer of the speech synthesizing integrated circuit chip, an input/output port, and a sound data storage
memory;

the input/output port of the speech synthesizing integrated circuit chip being interfaced with the input/output port of the sound
synthesizing integrated circuit chip;

at least one of the integrated circuit chips being programmed to cause the microprocessor of the speech synthesizing integrated
circuit chip to retrieve speech data from the sound data storage memory of the sound synthesizing integrated circuit chip for speech
synthesis by the speech synthesizer of the speech synthesizing integrated circuit chip.

32. The speech synthesizing circuit of claim 31 wherein the sound synthesizing integrated circuit chip is programmed to cause the
microprocessor of the sound synthesizing integrated circuit chip to retrieve sound data from the sound data storage memory of the
sound synthesizing integrated circuit chip for sound synthesis by an adaptive pulse code modulation synthesizer of the sound
synthesizing integrated circuit chip.

33. The speech synthesizing circuit of claim 31 wherein the speech synthesizing integrated circuit chip is selected from the family of
TSP50C4X, TSP50C1X, and TSP50C3X chips.

34. The speech synthesizing circuit of claim 33 wherein the speech synthesizing integrated circuit chip comprises a TSP50C3X chip.

35. The speech synthesizing circuit of claim 31 wherein the sound synthesizing integrated circuit chip is selected from the family of
SPC40A, SPC256A, and SPC512A chips.

36. The speech synthesizing circuit of claim 31 wherein the speech synthesizer of the speech synthesizing integrated circuit chip is a
linear predictive coding speech synthesizer.

37. The speech synthesizing circuit of claim 31 wherein the sound synthesizer of the sound synthesizing integrated circuit chip is an
adaptive pulse code modulation sound synthesizer.

38. The speech synthesizing circuit of claim 31 wherein the speech synthesizing integrated circuit chip is programmed to cause the
microprocessor of the speech synthesizing integrated circuit chip to retrieve speech data from the sound data storage memory of the
sound synthesizing integrated circuit chip for speech synthesis by the speech synthesizer of the speech synthesizing integrated
circuit chip.

39. A method of combining a speech synthesizing integrated circuit chip and a sound synthesizing integrated circuit chip, comprising
the steps of:

providing a speech synthesizing integrated circuit chip having a microprocessor, a speech synthesizer, and an input/output port for
interfacing with an external memory;

providing a sound synthesizing integrated circuit chip having a microprocessor, a sound synthesizer having a data rate substantially
greater than that of the speech synthesizer of the speech synthesizing integrated circuit chip, an input/output port, and a sound data
storage memory;

interfacing the input/output port of the speech synthesizing integrated circuit chip with the input/output port of the sound synthesizing
integrated circuit chip; and

programming at least one of the integrated circuit chips to cause the microprocessor of the speech synthesizing integrated circuit
chip to retrieve speech data from the sound data storage memory of the sound synthesizing integrated circuit chip for speech
synthesis by the speech synthesizer of the speech synthesizing integrated circuit chip.

40. An audio synthesizing circuit, comprising:

a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
balanced speaker driver connected to receive an output of the audio synthesizer containing audio information and having two outputs
for connection of a first speaker impedance between the two outputs;

a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
single-ended speaker driver connected to receive an output of the audio synthesizer containing audio information and having a
single output for connection to a second speaker impedance; and

a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizing integrated circuit chip and
also connected to the single-ended speaker driver of the second audio synthesizing integrated circuit chip.

41. The audio synthesizing circuit of claim 40 wherein the first speaker impedance differs from the second speaker impedance.

42. The audio synthesizing circuit of claim 40 wherein the audio synthesizer of the first audio synthesizing integrated circuit produces
a pulse width modulated output.

43. An audio synthesizing circuit, comprising:

a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs;

a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
single-ended speaker driver having a single output for connection to a second speaker impedance;

a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizing integrated circuit chip and
also connected to the single-ended speaker driver of the second audio synthesizing integrated circuit chip, and

at least one resistor connected to the speaker so as to form a resistive network with the speaker, the resistive network having an
impedance between the two outputs of the balanced speaker driver equal to the first speaker impedance and having a single-ended
impedance connected to the output of the single-ended speaker driver equal to the second speaker impedance.

44. The audio synthesizing circuit of claim 43 wherein the resistor is connected in series with the speaker, and the output of the
single-ended speaker driver is connected to the junction between the resistor and the speaker.

45. The audio synthesizing circuit of claim 44 wherein the first speaker impedance is four times the second speaker impedance, and
wherein the resistor has a resistance equal to the resistance of the speaker.

46. An audio synthesizing circuit, comprising:

a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs;

a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
single-ended speaker driver having a single output for connection to a second speaker impedance; and

a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizing integrated circuit chip and
also connected to the single-ended speaker driver of the second audio synthesizing integrated circuit chip,

wherein the first and second audio synthesizing circuits are formed on respective integrated circuit chips.

47. An audio synthesizing circuit, comprising:

a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs;

a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
single-ended speaker driver having a single output for connection to a second speaker impedance; and

a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizing integrated circuit chip and
also connected to the single-ended speaker driver of the second audio synthesizing integrated circuit chip,

wherein the first audio synthesizing circuit comprises a speech synthesizing circuit and the second audio synthesizing circuit
comprises a non-speech sound synthesizing circuit.

48. An audio synthesizing circuit, comprising:

a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
balanced speaker driver having two outputs for connection of a first speaker impedance between the two outputs;

a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory, and a
single-ended speaker driver having a single output for connection to a second speaker impedance; and

a speaker connected between the two outputs of the balanced speaker driver of the first audio synthesizing integrated circuit chip and
also connected to the single-ended speaker driver of the second audio synthesizing integrated circuit chip,

wherein the audio driver of the second audio synthesizing integrated circuit produces an analog output.

49. A method of combining a plurality of audio synthesizing integrated circuits, comprising the steps of:

providing a first audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage memory,
and a balanced speaker driver connected to receive an output of the audio synthesizer containing audio information and having two
outputs for connection of a first speaker impedance between the two outputs;

providing a second audio synthesizing integrated circuit having a microprocessor, an audio synthesizer, an audio data storage
memory, and a single-ended speaker driver connected to receive an output of the audio synthesizer containing audio information and
having a single output for connection to a second speaker impedance; and

connecting a speaker between the two outputs of the balanced speaker driver of the first audio synthesizer and also connecting the
speaker to the single-ended speaker driver of the second audio synthesizer.

Description

REFERENCE TO MICROFICHE APPENDICES

Microfiche Appendices A-D are being submitted with the present application. Microfiche Appendices A-D have 23 frames, 8 frames,
35 frames, and 11 frames respectively, all of which are located on a single microfiche. A claim of copyright is hereby made by
Hasbro, Inc. with respect to the software code contained in Microfiche Appendices C and D, as of the date of first issuance of a U.S.
patent issued on this application. The copyright owner has no objection to the facsimile reproduction by anyone of Microfiche
Appendices C and D as they appear in the Patent and Trademark office patent file or records, but reserves all other copyright rights
whatsoever.

BACKGROUND OF THE INVENTION

The present invention relates in general to speech and sound synthesizing circuits and more particularly concerns techniques for
combining high-efficiency LPC speech synthesizing chips with the low-cost memory of ADPCM audio synthesizing chips.

One example of LPC (linear predictive coding) speech synthesizing chips is the Texas Instruments TSP50CXX family of LPC chips.
These chips are highly efficient in their use of stored speech data because their speech synthesizer models a tube of resonant
cavities corresponding to the human vocal cords, mouth, etc. Thus, these chips can synthesize speech at a low data rate. TSP50CXX
chips are described in the Texas Instruments Design Manual for the TSP50C0X/1X Family Speech Synthesizer and also in U.S. Pat.
Nos. 4,234,761, 4,449,233, 4,335,275, and 4,970,659.

An example of ADPCM (adaptive pulse code modulation) audio synthesizing chips is the Sunplus SPC40A, SPC256A, and SPC512A
family of chips. These chips produce speech and other sounds at a high data rate. The chips provide low-cost memory because the
chips compete with the LPC chips on a cost-per-second basis, and given that their data usage rate is higher than that of the LPC
chips by an order of magnitude, these chips must therefore be designed to achieve a cost per memory element that is lower than
that of the LPC chips by an order of magnitude. In addition, these chips do not include complex speech synthesis circuitry.

SUMMARY OF THE INVENTION

One aspect of the invention features a speech synthesizing circuit that includes a speech synthesizing integrated circuit chip and an
external memory integrated circuit chip. The speech synthesizing integrated circuit chip includes a microprocessor, a speech
synthesizer, a programmable memory, an input/output port, and a speech address register for storing an address containing speech
data. The speech synthesizing integrated circuit chip includes an instruction, pre-programmed into the speech synthesizing
integrated circuit chip during manufacture thereof, that causes an address to be loaded onto the speech address register. The
input/output port of the speech synthesizing integrated circuit chip is connected to the external memory integrated circuit chip. The
programmable memory of the speech synthesizing integrated circuit chip is programmed to cause the microprocessor to retrieve
speech data from the external memory integrated circuit chip for speech synthesis by the speech synthesizer. The programmable
memory is programmed by providing a software simulation of the instruction that causes an address to be loaded onto the speech
address register. The software simulation causes the address to be loaded into the external memory integrated circuit chip.

In certain embodiments the external memory is an audio data storage memory of an audio synthesizing integrated circuit chip that
could not ordinarily interface directly with the speech synthesizing integrated circuit chip. The software simulation makes it is
possible to retrieve speech data from a preferably relatively inexpensive external memory without the use a hardware interface,
thereby minimizing overall cost. The minimization of cost is especially important in certain electronic toys.

According to another aspect of the invention, the speech synthesizing integrated circuit chip includes one or more instructions,
pre-programmed into the speech synthesizing integrated circuit chip during manufacture thereof, that obtain speech data located at
an address stored in the speech address register. At least one of the integrated circuit chips is programmed to cause speech data to
be delivered from the external memory integrated circuit chip to the speech synthesizing integrated circuit chip for speech synthesis
by the speech synthesizer, by providing a software simulation of the one or more instructions that obtain speech data located at an
address stored in the speech address register. The software simulation causes speech data to be obtained by the speech
synthesizing integrated circuit chip from the external memory integrated circuit chip at an address stored in the external memory
integrated circuit chip.

According to another aspect of the invention, the speech synthesizing integrated circuit chip includes a linear predictive coding (LPC)
speech synthesizer and the external memory is the audio data storage memory of an audio synthesizing integrated circuit chip that
also includes a microprocessor, an adaptive pulse code modulation (ADPCM) synthesizer, a programmable memory, and an
input/output port. The programmable speech data retrieved from the audio data storage memory of the audio synthesizing integrated
circuit chip by the speech synthesizing integrated circuit chip is used for speech synthesis by the speech synthesizing integrated
circuit chip.

In certain embodiments the programmable memory of the audio synthesizing integrated circuit chip is programmed to cause the
microprocessor of the audio synthesizing integrated circuit chip to retrieve audio data (e.g., data for non-speech sounds such as
breaking glass, ringing bells, etc.) from the audio data storage memory of the audio synthesizing integrated circuit chip for audio
synthesis by the audio synthesizer of the audio synthesizing integrated circuit chip. In other embodiments the audio data from the
audio synthesizing integrated circuit chip is delivered to the speech synthesizing integrated circuit chip for speech synthesis by the
speech synthesizer.

The ability to combine the LPC speech synthesizing integrated circuit chip and the ADPCM audio synthesizing integrated circuit chip
is useful in certain electronic toys, in which the speech synthesizing integrated circuit chip produces speech while the audio
synthesizing integrated circuit chip produces non-speech sound effects. The sharing of speech data between the two integrated
circuit chips can be an efficient way to take advantage of a preferably relatively inexpensive memory on the audio synthesizing
integrated circuit chip and a preferably relatively efficient speech generation algorithm used by the speech synthesizing integrated
circuit chip. This makes it possible to provide extended speech at low cost.

According to another aspect of the invention, one of the integrated circuit chips includes a balanced speaker driver having two outputs
for connection of a first speaker impedance between the two outputs, and another of the integrated circuit chips includes a
single-ended speaker driver having a single output for connection to a second speaker impedance. A speaker is connected between
the two outputs of the balanced speaker driver of the first audio synthesizer and is also connected to the single-ended speaker driver
of the second audio synthesizer.

The connection of a single speaker to the balanced speaker driver and the single-ended speaker driver (with the use of an
appropriate resistance network to ensure that each driver "sees" an appropriate effective resistance to which it is connected) makes
it possible to combine audio effects from both integrated circuit chips (for example, speech from one chip and non-speech sound
effects from the other chip) with a single speaker, thereby minimizing cost. This minimization of cost is important in certain electronic
toys. The audio effects from the two integrated circuit chips can be combined simultaneously if the balanced speaker driver produces
a pulse width modulated output while the single-ended speaker driver produces an analog output.

Numerous other features, objects, and advantages of the invention will become apparent from the following detailed description
when read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of the Texas Instruments TSP50CXX family of speech synthesizing chips.

FIG. 2 is a block diagram of a Texas Instruments TSP50C1X speech synthesizing chip interfaced with an external memory chip
through a Texas Instruments TMS60C20-SE hardware interface chip.

FIG. 3 is a functional block diagram of a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip.

FIG. 4 is a block diagram of a circuit according to the invention combining a Texas Instruments TSP50CXX speech synthesizing chip
with a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip.

FIG. 5 is a listing of steps that utilize the LUAPS and GET instructions of a Texas Instruments TSP50CXX speech synthesizing chip
for synthesizing speech.

FIG. 6 is a listing of the steps performed by software simulations, according to the invention, of the steps in FIG. 5.

FIG. 7 is a listing of functions performed by certain input and output lines of a Texas Instruments TSP50CXX speech synthesizing
chip and a Sunplus SPC40A, SPC256A, or SPC512A chip combined together according to the invention.

FIG. 8 is a listing of commands that can be delivered from a Texas Instruments TSP50CXX speech synthesizing chip to a Sunplus
SPC40A, SPC256A, or SPC512A chip in accordance with the invention.

FIG. 9 is a timing diagram of a write operation in accordance with the invention.

FIG. 10 is a timing diagram of a read operation in accordance with the invention.

FIG. 11 is a flow chart of the operation of a Sunplus SPC40A, SPC256A, or SPC512A chip according to the invention.

DETAILED DESCRIPTION

With reference to FIG. 1, a Texas Instruments TSP50CXX speech synthesizing chip 10, such as a TSP50C1X or TSP50C3X chip,
includes an LPC-12 speech synthesizer circuit 12 (Linear Predictive Coding, 12-pole digital filter), which is capable of operating at a
speech sample rate ranging up to ten kilohertz or eight kilohertz (but typically at a data rate of only 1.5 kilobits per second for normal
speech), and a microcomputer 14 capable of executing up to 600,000 instructions per second. The microcomputer includes an
eight-bit microprocessor 16 with sixty-one instructions, a four-kilobyte, six-kilobyte, eight-kilobyte, sixteen kilobyte, or thirty-two-kilobyte
read-only memory 18 for storing program instructions for microprocessor 16 and for storing speech data corresponding to about
twelve, twenty, thirty, sixty, or one hundred and twenty seconds of speech, and an input/output circuit 20 for ten software-controllable
input/output lines (in the case of a TSP50C1X chip, seven lines for connecting the chip to an external memory or an interface adapter
for an external memory, as described below, and three arbitrary lines). Speech synthesizing chip 10 also includes a random-access
memory 22 having a capacity of sixteen twelve-bit words and either forty-eight or one hundred and twelve bytes of data, depending on
the model of the chip, an arithmetic logic unit 24, an internal timing circuit 26, for use in conjunction with microcomputer 14 and
speech synthesizer circuit 12, and a speech address register (SAR) 13 for storing addresses at which speech data is located.

In the case of a TSP50C1X chip, microcomputer 14 includes a built-in interface that enables microcomputer 14 to connect directly to
an optional external Texas Instruments TSP60C18 or TSP60C81 read-only memory that is designed to store speech data in addition
to the speech data stored in internal read-only memory 18 for use by speech synthesizer circuit 12 (a mode register in speech
synthesizer chip 10 contains a flag indicating whether data is to be retrieved from internal read-only memory 18 or an external
memory). This built-in interface includes input/output circuit 20 and seven of the input/output lines with which it is associated. The
built-in interface is controlled by the program in internal read-only memory 18.

Referring to FIG. 2, as an alternative to connecting a TSP50C1X speech synthesizing chip 10 directly to a TSP60C18 or TSP60C81
read-only memory, speech synthesizing chip 10 can interface with an arbitrary, industry-standard read-only memory 28 through an
external Texas Instruments TMS60C20-SE hardware interface chip 30. The connection between speech synthesizing chip 10 and
hardware interface chip 30 includes seven of the input/output lines of speech synthesizing chip 10, and the connection between
hardware interface chip 30 and read-only memory 28 includes about thirty-two lines. Thus, hardware interface chip 30 makes it
possible to connect speech synthesizing chip 10 to an external read-only memory 28 having more output lines than could otherwise
be connected to speech synthesizing chip 10. Hardware interface chip 30 is controlled by calls from the program in internal read-only
memory 18.

The structure of the Texas Instruments -TSP50C3X chips is similar to that of the TSP50C1X chips described above in connection
with FIGS. 1 and 2, except that the TSP50C3X chips do not include hardware for connecting to and obtaining data from an external
memory. An example of code provided by Texas Instruments for programming read-only memory 18 of a TSP50CXX speech
synthesizing chip is attached to this application as Microfiche Appendix A.

With reference to FIG. 3, a Sunplus SPC40A, SPC256A, or SPC512A audio synthesizing chip 34 contains a large microcontroller 36
that includes an eight-bit RISC controller 38, a-40, 256, or 512 kilobyte read-only-memory 40 for storing program instructions for
RISC controller 38 and for storing audio data corresponding to about twelve seconds of sound, and a 128-byte random-access
memory 42 for use in conjunction with RISC controller 38. Audio synthesizing chip 34 also includes an eight-bit digital-to-analog
converter 44 that functions as an audio synthesizer by converting data from read-only-memory 40 to analog signals and an internal
timing circuit 46 for coordinating operation of microcontroller 36 and digital-to-analog converter 44. A general input/output port 48 is
provided for connecting audio synthesizing chip 34 with external memory for storing additional audio data. Input/output port 48 has
sixteen pins in the case of an SPC40A chip, twenty-four pins in the case of an SPC256A chip, and eleven pins in the case of an
SPC512A chip.

Audio synthesizing chip 34 typically operates at a data rate of about 24 kilobits per second, which is much higher than the typical data
sample rate of the speech synthesizing chip described above in connection with FIG. 1. The speech synthesizing chip of FIG. 1 and
the audio synthesizing chip of FIG. 3 are of comparable price and both can store data corresponding to about twelve seconds of
sound. The audio synthesizing chip of FIG. 3 must store more data than the speech synthesizing chip of FIG. 1 because of the
difference in the data sample rates, and thus it can be said that the audio synthesizing chip of FIG. 3 uses a cheaper memory.

An examples of code provided by Sunplus for programming the read-only memory 40 of an SPC40A, SPC256A, or SPC512A audio
synthesizing chip is attached to this application as Microfiche Appendix B.

Referring to FIG. 4, in a circuit according to the present invention the input/output circuit 20 of a Texas Instruments TSP50CIX or
TSP50C3X speech synthesizing chip 10 is connected directly to the input/output port 48 of a Sunplus SPC40A, SPC256A, or
SPC512A audio synthesizing chip 34 by means of four input/output lines. The flow of audio data is illustrated by paths 50, 52, and 54.
In particular, speech synthesizer circuit 12 of speech synthesizing chip 10 receives speech data from read-only memory 18 of speech
synthesizing chip 10 along path 50 and also receives additional speech data from read-only memory 40 of audio synthesizing chip
34 along path 52. Digital-to-analog converter 44 of audio synthesizing chip 34 can receive non-speech audio data (e.g., music,
breaking glass, ringing bells) from read-only memory 40 of audio synthesizing chip 34 along path 54. Thus, speech synthesizer
circuit 12 receives more speech data than can be included in internal read-only memory 18, the additional speech data being
received from an external read-only memory 40 that is cheaper per unit of speech data than internal read-only memory 18. Because
digital-to-analog converter 44 does not include the LPC speech processing capabilities of speech synthesizer circuit 12, and
because speech synthesizer circuit 12 is not specifically designed for synthesizing non-speech sounds, it can be more appropriate
to direct non-speech data from read-only memory 40 to digital-to-analog converter 44 than speech synthesizer circuit 12. Both chips
10 and 34 can create sound effects at the same time, with chip 10 producing speech and chip 34 simultaneously producing
non-speech sound effects.

The flow of data along paths 50 and 54 is conventional in each of chips 10 and 34, but the flow of data along path 52 is obtained by
modifying the standard code for read-only memory 18 and the standard code for read-only memory 40 to permit the direct connection
between the two chips. An example of a code modification for read-only memory 18 of chip 10 is attached to this application as
Microfiche Appendix C and an example of a code modification for read only memory 40 is attached as Microfiche Appendix D.

The modification of the code in read-only memory 40 instructs the microprocessor of chip 34 to send speech data to input/output port
48 along path 52 rather than to digital-to-analog converter 44 along path 54. The flow of data along path 52 between chips 10 and 34
occurs through four input/output lines of each of chips 10 and 34. The four input/output lines may be, for example, lines PA0, PA1,
PA2, and PB1 of chip 10, and lines PD0, PD6, PD1, and PD4 respectively of chip 34.

The modification of the code in read-only memory 18 is a software simulation of the hardware "LUAPS" and "GET" instructions of chip
10 (hardware instructions are implemented by hard-wired gates or micro-code instructions programmed into a chip during
manufacture). With reference to FIG. 5, ordinarily, a desired start address of a speech segment is loaded into the A register of chip
10, and then the "LUAPS" instruction loads the address from the A register into the SAR register (Speech Address Register) on chip
10 and loads a parallel-to-serial register on chip 10 with the contents of the address contained in the SAR register. Then, each
successive "GET X" instruction transfers X bits from the parallel-to-serial register, to the A register of chip 10. The SAR register is
incremented every time the parallel-to-serial register is loaded, and whenever the parallel-to-serial register becomes empty, it is
loaded with contents of the address contained in the SAR register. The groups of bits obtained by the "GET" instructions form the
frames of LPC parameters described in detail in the above-mentioned Texas Instruments Design Manual and patents. In the
TSP50C1X chips, the address pointed to by the SAR register may be on-chip or off-chip (if a specially configured Texas Instruments
external memory is used), because the TSP50C1X chips include hardware for connecting to and obtaining data from a specially
configured Texas Instruments external memory. In the TSP50C3X chips the address pointed to by the SAR register must be on-chip.

With reference to FIG. 6, according to the present invention, a software simulation of the LUAPS and GET instructions of FIG. 5 is
provided. Instead of loading the address from the A register of the LPC chip into an SAR register as in the case of the LUAPS
instruction of FIG. 5, CALL STPNTR(X) causes pointer X to be stored in the ADPCM chip. Instead of loading a parallel-to-serial
register in the LPC chip with the contents of the address contained in an SAR register and transferring bits from the parallel-to serial
register to the A register of the LPC chip as in the case of the LUAPS and GET instructions of FIG. 5, CALL PREPGET P(X) prepares
the ADPCM chip to send to the LPC chip the data to which pointer X points, and CALL GET(Y) causes Y bits of data pointed to by
pointer X to be read from the ADPCM chip. In one embodiment, up to three pointers are used, so that data can be read from up to
three sets of storage locations corresponding to three different sounds to be produced simultaneously by the LPC chip (for example,
music with three-part harmony).

With reference to FIG. 7, according to the input/output structure of the LPC chip provided by the invention, the interface operation is
accomplished over four wires and is a command-driven structure. All commands are initialized on the side of the LPC chip and the
ADPCM chip is slave to the requested operations. Lines PA0-2 provide command codes to the ADPCM chip, and line PB1 indicates
to the ADPCM chip that there is a command on lines PA0-2. The LPC chip drops command strobe line PB1 after setting up a
command on lines PA0-2, and the ADPCM chip responds by executing the command that was strobed. Thus, the processor of the
LPC chip initiates each command and the processor of the ADPCM chip executes that command.

The various commands are shown in FIG. 8. Commands 1-3 indicate that data pointer 1, 2, or 3 is to be sent to the ADPCM chip (this
corresponds to CALL STPNTR(X)), and commands 4-6 indicate that data to which pointer 1, 2, or 3 points is to be read from the
ADPCM chip (this corresponds to CALL PREPGET P(X). In one particular embodiment useful in certain toys, command 0 instructs
the ADPCM chip to strobe one of eight strobe outputs to a game keyboard.

Referring again to FIG. 7, once the ADPCM chip has received the appropriate command, line PA0 is used to read data from the
ADPCM chip or send a pointer to the ADPCM chip, and line PA1 is used to clock the data serially into or out of the LPC chip. The
ADPCM processor maintains address pointers and counter that are advanced on clock events received on line PA1. Line PA2 is
used as a handshake signal during the process of reading data from the ADPCM chip.

With reference to FIG. 9, the LPC processor will perform CALL STPNTR(X) by placing a "Write Pointer X" command on lines PA0-PA2
and lowering strobe line PB1. After a period of time sufficient for the ADPCM chip to read the command has elapsed, the LPC chip
provides the first bit of data on line PA0 and then drops the clock signal on line PA1. During the clock low time the ADPCM chip will
accept and read in the bit on line PA0, and then the next bit of data is placed on line PA1, and so on. Operations that write data from
the LPC processor to the ADPCM processor are done without a handshaking signal. The data is clocked out by a fixed clock cycle.
The clock cycle time is the minimum time required for the ADPCM chip to reliably clock in the data. The LPC processor completes the
operation by raising strobe line PB1 high.

When the ADPCM chip detects a "Write Pointer X" command it will expect up to sixteen clocked data bits. When the operation is
complete the ADPCM chip stores the received value as Pointer X. It is possible to clock in fewer than sixteen bits of data to specify an
address. In particular, the first bit read out is the first bit of the address, and once strobe line PB1 goes high, the unclocked data bits
are all assumed to be zeros.

The timing diagram of FIG. 9 is also used in connection with the "Write Keyboard Strobe" command (Command 0 in FIG. 8). When
the ADPCM chip detects a "Write Keyboard Strobe" command it will expect a clocked data bit to specify the next output state. Once
strobe line PB1 goes high, the ADPCM chip drives the strobe lines to the proper value. In this way, the LPC chip controls eight
outputs of the ADPCM chip, and thus the interface between the LPC and ADPCM chips effectively increases the number of
input/output lines available to the LPC chip.

With reference to FIG. 10, operations that read data from the ADPCM chip to the LPC chip involve a handshaking signal on line PA2.
The "Read Data from Pointer X" commands (see discussion of FIG. 8 above) require line PA2 to be high, which is necessary in order
for handshaking to proceed correctly. This is because line PA2 is configured as an open-drain output at initialization, externally pulled
high by a 10K resistor.

When the LPC processor performs CALL PREPGET P(X) in order to prepare to read data, the LPC chip issues a "Read Data from
Pointer X" command on lines PA0-1 and then lowers strobe PB1. In response to the command, the ADPCM chip switches from its
default input mode to an output mode with respect to lines PA0 and PA2 of the LPC chip (consequently, for a brief period of time, line
PA0 of the LPC chip will receive output signals from both the LPC chip and the ADPCM chip). The ADPCM chip then acknowledges
acceptance of the command by pulling low line PA2 of the LPC chip. The LPC chip then performs CALL GET(Y) by setting line PA0 to
an input, lowering line PA1 to start the clocking of data, and raising strobe line PB1 to indicate to the ADPCM chip that the LPC chip is
ready to receive data. The ADPCM chip places the first bit of data on line PA0 and releases line PA2. The LPC chip reads the data
and raises the clock signal on PA1 to signal that the data has been read. The ADPCM chip responds by advancing an internal bit
counter and pulling line PA2 low to acknowledge receipt of the clock signal, and the LPC chip then responds by lowering line PA1 to
start the clocking of the next bit of data. The ADPCM chip then places the next bit of data on line PA0 and releases line PA2, and the
process continues until the LPC chip has received as much data as it wants. The LPC processor completes the operation by raising
strobe line PB1 high after Y bits of data have been received.

The four-wire interface between the two chips may also be used to transfer non-speech data in either direction between the LPC
RAM and the ADPCM RAM, in a manner similar to the timing diagrams of FIGS. 9 and 10, in order to effectively expand the amount of
RAM available to the master chip (the LPC chip in the embodiments described above).

FIG. 11 is a flow chart of the operation of the ADPCM chip. The ADPCM chip watches for strobe line PB1 of the LPC chip to go down
(step 100), and when this happens the ADPCM chip receives a read or write command on lines PA0-PA2 of the ADPCM chip (step
102), handles the read command (step 104; FIG. 10) or write command (step 106; FIG. 12), and then returns to step 100.

In another alternative embodiment, the ADPCM chip can be set up as the master microcontroller, and the LPC chip can function as
the slave. In this embodiment there is no need to perform a software simulation of the LUAPS instruction of the LPC chip, because
the pointers to the data in the ADPCM chip all originate from the ADPCM chip itself. It will now be apparent to those skilled in the art
that data can be transferred from the ADPCM chip to the LPC chip according to a technique similar to the technique shown in the
timing diagram of FIG. 10 (the initial synchronization process at the beginning of the timing diagram would differ but then the actual
data transfer process could proceed in a manner similar to that shown in FIG. 10). Thus, a type of software simulation of the LUAPS
and GET instructions of the LPC chip can be performed, even though the LPC chip in this particular embodiment functions as a
slave.

With reference to FIG. 4, the outputs of speech synthesizer circuit 12 of chip 10 and digital-to-analog converter 44 of chip 34 are
connected to a single speaker 56. The output of speech synthesizer circuit 12 is a pulse-width-modulated push-pull bridge balanced
drive for a 32-ohm speaker, and the output of digital-to-analog converter 44, amplified by transistor 58, is a single-ended drive for an
8-ohm speaker. The output of digital-to-analog converter 44, amplified by transistor 58, is connected to a node between 16-ohm
speaker 56 and 16-ohm resistor 60. Thus, the output of digital-to-analog converter 44 is connected to two parallelly connected
16-ohm resistances, or, in other words, an 8-ohm single-ended resistance. At the same time, the output of speech synthesizer circuit
12 is connected to two series-connected 16-ohm resistances, or, in other words, a 32-ohm resistance.

When speech synthesizer 12 is silent, its push-pull bridge balanced drive goes to low impedance, and the two outputs 62 and 64 of
the push-pull bridge balanced drive are at a positive voltage. This makes it possible for current to pass from output 62, through
speaker 56, and through amplifier 58 while audio synthesizer integrated circuit chip 34 is operating.

When chip 34 is silent, transistor 58 goes to high impedance (i.e., transistor 58 switches off). Meanwhile, pulse width modulated
current may pass between outputs 62 and 64 of the push-pull bridge balanced drive of speech synthesizer 12 through speaker 56
while speech synthesizer 12 is operating.

It is possible for both of chips 10 and 34 to operate simultaneously with the single speaker 56 because, when chip 10 is operating,
output 62 of speech synthesizer 12 pulses high and low, and whenever output 62 is high, current can pass from output 62 through
transistor 58 to produce the audio sounds synthesized by chip 34. The frequency of on and off pulsing of output 62 is too fast to affect
the perceived sound output produced by chip 34.

There has been described novel and improved apparatus and techniques for speech and sound synthesizing. It is evident that those
skilled in the art may now make numerous uses and modifications of and departures from the specific embodiment described
herein without departing from the inventive concept.

* * * * *

snakeplkn
06-09-2002, 11:04 PM
Hats off to N-2PF for solving the mystery once and for all!

Snake Plissken
"Call me Snake"

scruffziller
06-09-2002, 11:07 PM
What the heck did they mean "WIZARDS" on the Anikin chip?

JediTricks
06-10-2002, 02:14 AM
Snake, that's the same ones we had listed on the old forums too. There are apparently a few alternate patents filed for confusion's sake as well. ;)

I don't remember the chip dialogue from Ani's chips, but "Wizard!" was a line of his cut from the film and Kitster still says it. It's an old slang term from the '40s like "gee whiz!".

scruffziller
06-10-2002, 01:11 PM
Originally posted by JediTricks
Snake, that's the same ones we had listed on the old forums too. There are apparently a few alternate patents filed for confusion's sake as well. ;)

I don't remember the chip dialogue from Ani's chips, but "Wizard!" was a line of his cut from the film and Kitster still says it. It's an old slang term from the '40s like "gee whiz!".

I got this fig before the movie came out and I thought that he might have been talking about Obi Wan and Qui Gonn from possibly seeing them perform their Jedi powers.

Jedi Kit Fisto
06-18-2002, 02:58 PM
Count me in as someone who liked the CTCs

I bought an entire set of them on ebay last year,
and also picked up a store display CT reader for
a fair price.

Id like to get an example of one of the 'never released'
design if it ever comes up on ebay or at a show